# Digital Systems: From Logic Gates to Processors Coursera Quiz Answers

### All Weeks Digital Systems: From Logic Gates to Processors Coursera Quiz Answers

This course gives you a complete insight into the modern design of digital systems fundamentals from an eminently practical point of view. Unlike other more “classic” digital circuits courses, our interest focuses more on the system than on the electronics that support it. This approach will allow us to lay the foundation for the design of complex digital systems.

You will learn a set of design methodologies and will use a set of (educational-oriented) computer-aided-design tools (CAD) that will allow you not only to design small and medium-size circuits but also to access higher-level courses covering so exciting topics as application-specific integrated circuits (ASICs) design or computer architecture, to give just two examples.

#### Digital Systems: From Logic Gates to Processors Coursera Quiz Answers

#### Week 1: Digital Systems: From Logic Gates to Processors

#### Quiz 01: Numeration systems

Q1. In pure binary numeration system, how many bits do we need to represent the decimal value of 51210?:

- 9
- 8
- 11
- 10

Q2. In pure binary numeration system, with n = 6 bits, how many different combinations can be represented?:

**64**- 63
- 31
- 32

Q3. In pure binary numeration system, with n = 4 bits, we can represent any natural number between the values:

- [0,8]
- [-7,7]
**[0,15]**- [-7,8]

Q4. In pure binary numeration system, with n = 6 bits, how is represented the value 6210?.

Enter the 6-digit number without spaces. Example: 101010

Enter answer here

Q5. What is the radix-10 (decimal system) representation of the number 0101101012?.

Enter the number with 3 digits without spaces. Example: 212

Enter answer here

Q6. What is the radix-16 (hexadecimal system) representation of the number 100111012?.

Enter the number with 2 digits without spaces. Example: A3

Enter answer here

Q7. What is the pure binary representation of the number in radix-16 (hexadecimal system) F0E116?.

Enter the number with 16 digits without spaces. Example: 1011010100110010

Enter answer here

Q8. Given two natural numbers in binary representation, X = 01111102 and Y = 11101112 , what is the binary representation of X+Y?.

Enter the number with 8 digits without spaces. Example: 10010011

Enter answer here

Q9. Given two natural numbers in binary representation, X = 1000010012 and Y = 100111002 , what is the binary representation of X – Y?.

Enter the number with 7 digits and no spaces. Example: 1001001

Enter answer here

Q10. Given two natural numbers in in radix-16 (hexadecimal system) representation, X = 3CF16 and Y = FD216 , what is the radix-16 (hexadecimal system) representation of X+Y?.

Enter the number with 4 digits and no spaces. Example: A35B

Enter answer here

#### Quiz 02: Pseudocode

Q1. If we have the following description in pseudocode, which will be the value of the variable Y after line 6?

Enter a 1-digit integer number. Example: 8

`1 X <= 1;`

2 Y <= 2;

3 Z <= 3;

4 X <= X·Z;

5 Z <= X - Y;

6 Y <= X + Y + Z;

Enter answer here

Q2. Given the following pseudocode, which values will the variables a, b, c and d have after the execution of the algorithm?.

Write

the results separated by a blank space. Example: if the result at the

end of the execution is a = 1, b = 2, c = 23, d = 4, you should answer 1

2 23 4

`a <= 5; b <= 2; c <= 4; d <= 6; If (a > 0) AND (c > d) then`

a <= d + c;

else a <= d * c;

end if;

c <= d + a;

If b = c then

c <= c + b;

else c <= c – a;

end if;

Enter answer here

Q3. Which of the following pseudocodes implements the algorithm that calculates the addition of the even numbers between 1 and 103?

`A <= 2, sum <= 0;`

While A < 102 then

sum <= sum + A;

A <= A+2;

end while;

`A <= 2, sum <= 0;`

While A ≤ 103 then

sum <= sum + A;

A <= A+2;

end while;

`A <= 1, sum <=0;`

While A < = 103 then

sum <= sum + A;

A <= A+2;

end while;

`A <= 1, sum <= 0;`

While A < 102 then

sum <= sum + A;

A <= A+2;

end while;

Q4. Which of the following pseudocodes implements the algorithm that calculates the addition of the squares of the first 100 natural numbers (from 1 to 100 both included)?.

`total <= 0;`

For num in 1 to 100 loop

total <= num + (num)^2;

end loop;

`total <= 1;`

For num in 1 to 99 loop

total <= total + (num)^2;

end loop;

`For num in 1 to 100 loop`

total <= total + (num)^2;

end loop;

`total <= 0;`

For num in 1 to 100 loop

total <= total + (num)^2;

end loop;

Q5. Which of the following pseudocodes implements the algorithm that calculates the factorial of a number N?

`factorial <= 1;`

While N ≥ 0 loop

factorial <= factorial * N;

N <= N – 1;

end while;

`factorial <= 1;`

While N ≠ 0 loop

factorial <= factorial · N;

N <= N + 1;

end while;

`factorial <= 1; While N > 0 loop`

factorial <= factorial * N;

N <= N – 1;

end while;

`factorial <= 1; While N > 0 loop`

factorial <= factorial * N;

N <= N + 1;

end while;

Q6. Given two 8-component vectors: [a0, a1, ……a7] and [b0, b1, ……b7] which of the following pseudocodes computes Y = a0 + b0 + a1 + b1 +…… + a7 + b7 ?

`for i in 0 to 7 loop`

acc <= acc + ai + bi;

end loop;

Y <= acc;

`acc <= 0;`

for i in 0 to 7 loop

acc <= acc + ai · bi;

end loop;

Y <= acc;

`acc <= 0;`

for i in 0 to 7 loop

acc <= acc + ai + bi;

end loop;Y <= acc;

`for i in 1 to 8 loop`

acc <= acc + ai + bi;

end loop;

Y <= acc;

Q7. What will be the value of variable a at the end of the algorithm?

Write the solution as a 2-digit integer number. Example: 59

`a <= 35;`

For i in 0 to 4 loop

For j in 0 to 4 loop

If (i=j) then a <= a + 1;

elsif (j = 4) then a <= a + 2;

end if;

end if;

end loop;

end loop;

a <= a + 10;

Enter answer here

#### Quiz 03: Graded quiz

Q1. Which of the following statements are true? Check all that apply.

- Any digital system can be specified using a functional description or a structural description.
- The functional description of a digital system depicts its internal structure.
- Any block in a digital circuit can be described hierarchically until a level of simplicity that allows its synthesis using a predefined catalog of components is achieved.
- All blocks of a hierarchical description must be specified by the same type of description (functional or structural).

Q2. In a stress test for elite athletes a physical system is used to measure the performance of the individual. Indicate which of these signals are analog signals:

- Activity level (accelerometer) ⇒ Type: Current, Range: [0-7 mA]
- Temperature ⇒ Type: Temperature, Range: from 18ºC to 22ºC (only integer and half-integer values are measured)
- O2 Saturation ⇒ Type: Voltage, Range: [1-5 mV]
- Respiratory Rate ⇒ Type: Numerical; Range: integers from 8 to 40.
- VO2 ⇒ Type: Liters / minute; Range: [2-7.5 l / min].
- Performance ⇒ Type: Real number; Range: [0-1]

Q3. Following the previous question, indicate which of the following signals are digital signals.

- Temperature ⇒ Type: Temperature, Range: from 18ºC to 22ºC (only integer and half-integer values are measured)
- O2 Saturation ⇒ Type: Voltage, Range: [1-5 mV]
- Heart rate ⇒ Type: Numeric; Range: Integers from 35 to 300
- Performance ⇒ Type: Real number; Range: [0-1]
- ECG (Electrocardiogram) ⇒ Type: Voltage; Range: [0.5-4 mV].
- Alarm ⇒ Type: Binary digit; Range: {0,1}.

- A
- B
- C
- D
- E
- F

Q5. The pseudocode shown in figure functionally describes the chronometer of lesson 2.1.The update procedure updates the values of h, m, s and t whenever a clock pulse arrives (ref_positive_edge signal).

Which of the following pieces of pseudocode correctly implement the update procedure?. Mark all that apply.

`1 loop`

2 if reset=ON then h <= 0; m <= 0; s <= 0; t <= 0;

3 else if start = ON then

4 while stop = OFF loop

5 if ref_positive_edge = TRUE then update(h, m, s, t);

6 end if;

7 end loop;

8 end if;

9 end if;

10 end loop;

`1 t <= t + 1;`

2 if t = 10 then t <= 0;add_one_second <= 1;

3 else add_one_second <= 0;

4 end if;

5 s <= s + add_one_second;

6 if s = 60 then s <= 0; add_one_minute <= 1;

7 else add_one_minute <= 0;

8 end if;

9 m <= m + add_one_minute;

10 if m = 60 then m <= 0; add_one_hour <= 1;

`1 if t = 9 then t <= 0; add_one_second <= 1;`

2 else add_one_second <= 0;

3 end if;

4 t <= t+1;

5 if s = 60 then s <= 0; add_one_minute <= 1;

6 else add_one_minute <= 0;

7 end if;

8 s <= s + add_one_second;

9 if m = 60 then m <= 0; add_one_hour <= 1;

10 else add_one_hour <= 0;

`1 t <= t + 1;`

2 if t = 10 then t <= 0; s <= s + 1; end if;

3 if s = 60 then s <= 0; m <= m + 1; end if;

4 if m = 60 then m <= 0; h <= h+1; end if;

5 if h = 24 then h <= 0; end if;

Q6. Consider a system with three input signals:

- ref, a square wave with a period of 1 microsecond(1), and
- two natural number a and b

The system generates a square wave, f, with period equal to (a + b) microseconds, as shown in figure.

**Which of the following algorithms describe the system?**

(1) Variable “ref_positive_edge” takes the value TRUE when a positive edge of signal “ref” arrives, and FALSE otherwise.

1 loop

2 f <= 1; count <= 0;

3 for i in 1 to a loop

4 if ref_positive_edge = TRUE then count <= count + 1;

5 end if;

6 end loop;

7 f <= 0; count <= 0;for i in 1 to b loop

8 if ref_positive_edge = TRUE then count <= count + 1;

9 end if;

10 end loop;

1 loop

2 f <= 1; count <= a; while count > 0 loop

3 if ref_positive_edge = TRUE then count <= count – 1; end if; end loop; f <= 0; count <= b; while count > 4 0 loop

5 if ref_positive_edge = TRUE then count <= count – 1;

6 end if;

1 loop

2 f <= 1; while count > 0 loop

3 if ref_positive_edge = TRUE then a <= a – 1; end if; end loop; f <= 0; while count > 0 loop

4 if ref_positive_edge = TRUE then b <= b – 1;

5 end if;

Q7. Mark the correct statement:

- Digital electronic systems only work with supply voltages of 0 and 1V.
- In CMOS circuits (circuits built with CMOS gates) logical values of 1 and 0 are defined as the passage or non-passage of current, respectively.
- Logical values of 0 and 1 are defined as a voltage close to 0 V and a voltage close to the circuit supply voltage respectively.
- In a 5V powered circuit, the logical value 1 is defined as a voltage of exactly 5V.

Q8. Fill in the above table so that it describes the behavior of the following circuit:

(Enter the 0s and 1s separated by a blank. For example, if the result was the one shown below, the answer should be 0 0 1 1 0 0 1 0)

Enter answer here

#### Week 2: Digital Systems: From Logic Gates to Processors

Q1. We want to use a ROM memory to implement a digital circuit that receives two 2-bit numbers XX and YY (XX=x1x0, YY=y1y0) and detects whether XX is greater (G = 1G=1), lower (L = 1L=1) or equal (E = 1E=1) to YY. What information must be stored in the memory address words 1001 and 1111?

Note: The most significant bit of the address bus is x1.

- 110, 100
- 100, 010
- 100, 001
- 001, 101

Q2. Let f(a,b,c,d,e)f(a,b,c,d,e) be a Boolean function. Check which expression corresponds to the minterm 9 (m_{9} of the function.

a. \overline {b}. \overline {c}. \overline {d}.\overline {e}*a*.*b*.*c*.*d*.*e*

a. \overline {b}. \overline {c}. d.\overline {e}*a*.*b*.*c*.*d*.*e*

\overline {a}. b. \overline {c}. \overline {d}.e*a*.*b*.*c*.*d*.*e*

a.b.c.d.e*a*.*b*.*c*.*d*.*e*

Q3. Note: You will need to use VerilUOC_Desktop to answer this question. Please, complete the module “VerilUOC_Desktop tools”, inside this week 2, before performing this exercise.

Minimize the Boolean function as a sum of products of literals:

*f*(*a*,*b*,*c*,*d*,*e*)=(*b*+*a*.*c*.*d*).((*b*+*c*+*d*)+*c*.*d*)+*a*.*c*.*d*.*e*

**Instructions to answer this question**

1) In the virtual machine, open VerilUOC_Desktop, click on “Simulate”->”Verification” and then click on the BoolMin tab.

2) In “Module”, select “Graded Exercises” and click on exercise 2.3.b. Enter the minimized Boolean expression.

3) BoolMin returns a 4 uppercase letters code. Type it in the answer box.

Enter answer here

Q4. Note: You will need to use VerilUOC_Desktop to answer this question. Please, complete the module “VerilUOC_Desktop tools”, inside this week 2, before performing this exercise.

Draw a digital circuit that implements the following Boolean function **(do not simplify the function)**

*f*(*a*,*b*,*c*,*d*)=*a*.(*d*+*b*.*c*)+*c*.(*d*+*a*.*b*)

Inputs and outputs must be named respectively as a, b, c,d and f; all of them lower case.

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.*

*2) Click on “Simulate”->”Verification” and then click on the VerilCirc tab.*

*3) In “Module” select “Graded Exercises” and click on exercise 2.4.a.*

*4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q5. Note: You will need to use VerilUOC_Desktop to answer this question. Please, complete the module “VerilUOC_Desktop tools”, inside this week 2, before performing this exercise.

Write the Boolean expression implemented by the following circuit **(do not simplify the function):**

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop, click in “Simulate” -> ”Verification” and then click in the BoolMin tab.*

*2) In “Module” select “Graded Exercises” and click on exercise 2.5.a. Enter the Boolean expression.*

*3) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q6. Questions 6, 7 and 8 are interrelated and aim to see how Boolean algebra allows us to obtain simple combinational circuits.

**Identify which of the Boolean expressions below implements the following circuit:**

(*a*+*b*).((*a*+*b*).(*e*+*a*.*c*)+*d*.(*e*+*a*.*c*))

(a+b).((a+b)+(e+\overline{a}.c))+d.(e+\overline{a}.c)(*a*+*b*).((*a*+*b*)+(*e*+*a*.*c*))+*d*.(*e*+*a*.*c*)

(a+b).(e+\overline{a}.c)+d.(e+\overline{a}.c)(*a*+*b*).(*e*+*a*.*c*)+*d*.(*e*+*a*.*c*)

(a+b).(a+b).(e+\overline{a}.c)+d.(e+\overline{a}.c)(*a*+*b*).(*a*+*b*).(*e*+*a*.*c*)+*d*.(*e*+*a*.*c*)

Q7. Note: You will need to use VerilUOC_Desktop to answer this question. Please, complete the module “VerilUOC_Desktop tools”, inside this week 2, before performing this exercise.

Questions 6, 7 and 8 are interrelated and aim to see how Boolean algebra allows us to obtain simple combinational circuits.

Simplify the boolean function obtained in the previous question **as a sum of products of literals.**

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop, click in “Simulate”->”Verification” and then click in the BoolMin tab.*

*2) In “Module”, select “Graded Exercises” and click on exercise 2.7.b. Enter the minimized Boolean expression.*

*3) BoolMin returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q8. Questions 6, 7 and 8 are interrelated and aim to see how Boolean algebra allows us to obtain simple combinational circuits.

Draw the circuit that implements the minimized Boolean expression obtained in question 6 and indicate how many AND, OR and INV gates are required. There is no restriction in the number of inputs of the AND and OR gates, use gates with as many inputs as you need.

Write the answer as 3 integer numbers separated by a whitespace, in this order: number of AND gates, number of OR gates and number of inverters. For instance, if 4 AND gates, 1 OR and 3 inverters were required, the answer should be 4 1 3

**See how this circuit, equivalent to the one in question 6, requires fewer gates than the original.**

Enter answer here

#### Week 3: Digital Systems: From Logic Gates to Processors

Q1. In n=4, what set(s) of cube(s) is(are) equivalent to the set {0000, 0010, 01×1, 0110, 1000, 1010}? (equivalent= they cover the same set of minterms)

- 1×00, 0x01, 10xx
- x00, x01, 0x1
- x0x0, 01×1, 011x
- 11×0, 1×01, 10×1

Q2. Design a circuit to compare two 2-bit numbers **A **and **B (A = a1 a0; B = b1 b0)**. The circuit has three outputs G (greater than), E (equal to) and L (less than) so that:

**G = 1 if A > B,****E = 1 if A = B, and****L = 1 if A < B.**

Note: Inputs to the circuit must be named as a1, a0, b1, b0, G, E and L. Respect upper and lower cases.

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.*

*2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.*

*3) In “Module” select “Graded Exercises” and click on exercise 3.2.a.*

*4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q3. Design a digital circuit that receives a 4 bits BCD-coded(*) number **X = abcd** and returns a signal **M7=1 if X ≥ 7**, and **M7=0** otherwise. The algorithm below shows the functional description of the circuit (“dc” means a “don’t care” combination).

Inputs and outputs of the circuit must be named as: a, b, c, d, and M7. Respect the upper and lowercases.

(*): BCD code (Binary Coded Decimal) encodes any base-10 number from 0 to 9 in base-2, using 4 bits. That is, 0 is coded by 0000, 1 by 0001, 2 by 0010 and so on until 9, which is encoded by 1001. Base-10 numbers higher than 9 require at least 2 digits and, consequently, they will never enter to the circuit.

```
1 if X > 1001 then M7<=dc;
2 else if X > 0110 then M7<=1;
3 else M7<=0;
4 end if;
5 end if;
```

__Instructions to answer this question__

*1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.*

*2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.*

*3) In “Module” select “Graded Exercises” and click on exercise 3.3.a.*

*4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q4. Patients admitted to the Observation Room of a hospital are continuously monitored by an electronic system that generates, every 5 seconds, four signals x0, x1, x2 and x3 with the following information:

- x0 and x1 indicate which parameter is being measured, as shown in Table 1
- x2 and x3 specify if the value of the parameter measured (indicated by x0, x1) is appropriate, high or low (see Table 2)

The alarm system receives these 4 bits and generates an alarm signal (ALARM = 1) when one or more of the following situations happen:

- SBP is high
- DBP is high or low
- HR is high or low
- SatO2 is low

**Design this alarm circuit.**

(Note: Inputs and outputs of the circuit must be named as x0, x1, x2, x3, and ALARM. Respect upper and lower cases)

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.*

*2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.*

*3) In “Module” select “Graded Exercises” and click on exercise 3.4.a.*

*4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q5. The following circuit consists of 8 identical components with 2 inputs “a” and “b”, and 2 outputs “c” and “d”. The maximum propagation time from inputs “a” or “b” to outputs “c” or”d” is equal to 0.5 ns. **Which is the maximum propagation time from any input to any output (in ns.)?**

Introduce the answer in nanoseconds, with 1 fractional digit. Examples: If the propagation time is 8.9 ns., introduce 8.9; if the propagation time is 6 ns., introduce 6.0

Preview will appear here…

Enter math expression here

Q6. Indicate which circuit implements the function f(a,b,c,d)=\Sigma (m_1, m_2, m_4, m_8, m_{11})*f*(*a*,*b*,*c*,*d*)=Σ(*m*1,*m*2,*m*4,*m*8,*m*11).

(example: m_{11}=a.\overline{b}.c.d*m*11=*a*.*b*.*c*.*d*)

Q7. *(This exercise and the next one refer to the same statement)*

Consider a system with three input signals x, y and max and one output signal z. All signals are binary encoded non-negative integers.

System specification:

- if (x – y) belongs to the interval 0 ≤ x – y ≤ max, then z = x – y;
- if (x – y) > max, then z = max;
- if (x – y) < 0, then z = 0.

Assume that a procedure difference(A, B, s, C) has been previously defined, where A, B and C are non-negative integers and s is a 1-bit number, so that it computes the difference A – B under the form A – B = (-1)s•C (s is the sign and C is the absolute value of the result).

**Which of the following algorithms properly describes the system?**

`1 difference(x, y, a, b);`

2 difference(max, b, c, d);

3 if c = 1 then e <= max; else e <= b; end if;

4 if a = 1 then z <= 0; else z <= e; end if;

`1 difference(x, y, a, b);`

2 difference(max, b, c, d);

3 if c = 1 then e <= max; else e <= b; end if;

4 if a = 1 then z <= 0; else z <= d; end if;

`1 difference(x, y, a, b);`

2 difference(max, b, c, d);

3 if c = 1 then e <= max; else e <= d; end if;

4 if a = 1 then z <= 0; else z <= e; end if;

Q8. *(Let’s continue with the last question)*

Assume that a module implementing the procedure difference(A, B, s, C) exists. If x and y are 4-bit numbers, which of the following circuits implements the desired system?

#### Week 4: Digital Systems: From Logic Gates to Processors

Q1. These exercises do not score in the final grade. Therefore, you can freely discuss them in the Forum without worrying about whether you are transgressing the Honor Code.

The algorithm in figure 1 computes P = X•Y where X and Y are n-bit and m-bit numbers respectively. The first step to implement the algorithm is to build a basic module that executes the “OnebitMultiplier” procedure (figure 2).

**What circuit implements the basic component shown in figure 2?**

(*hint*: \small(a \ NAND \ b) \ NAND \ (c\ NAND \ d) \ NAND \ (e \ NAND \ f) = a.b + c.d + e.f)(*a**N**A**N**D**b*) *N**A**N**D* (*c**N**A**N**D**d*) *N**A**N**D* (*e**N**A**N**D**f*)=*a*.*b*+*c*.*d*+*e*.*f*)

```
1 acc <= 0;
2 for i in 0 to m-1 loop
3 carry(0) <= 0;
4 for j in 0 to n-1 loop
5 OnebitMultiplier (acc(i+j), x(j), y(i), carry(j), next_a,
6 next_c);
7 acc(i+j) <= next_a; carry(j+1) <= next_c;
8 end loop;
9 acc(i+n) <= carry(n);
10 end loop;
11 P <= acc;
-------------
12 OnebitMultiplier (a, x, y, c, next_a, next_c)
13 --Attention: “.”, “+” y “⊕” represent the boolean functions AND,
14 --OR and XOR.
15 next_c <= a . c + a . (x . y) + c. (x . y);
16 next_a <= a ⊕ (x . y) ⊕ c;
17 end;
```

Figure 1

Figure 2: 1-bit multiplier

Q2. Let us continue with the algorithm of figure 1 in the previous question: The second step would be to properly connect n 1bM modules to implement the inner “for…loop” structure, and then to repeat the resultant framework m times to implement the outer “for…loop” structure.

Draw (on paper) a circuit implementing the complete algorithm for** n=4** and **m=3**, and answer the following question: **How many 1bM modules are required?** The answer must be an integer number.

Example: The above figure shows the resulting circuit for n=2 and m=2 (answer would be 4). To facilitate understanding, the iteration executed by every module has been written inside the box.

Figure 1: Multiplier for n=m=2

Enter answer here

Q3. Let’s continue with the previous question: If the maximum inputs-to-outputs delay of the 1bM is 0.25ns, **what is the propagation time, in ns., of the complete multiplier when n=5, m=2?**

Answer must be a 2-fraccional digits number. Example: 6.50

Enter answer here

Q4. Which of the following statements are true? Check all that apply.

- The “architecture” unit may describe the circuit with components of a library.
- Assignments A:=B; B:=A; interchange the values of A and B.
- The “Entity” unit describes the behavior of the circuit, but not its architecture.
- Concurrent statements are executed simultaneously.

Q5. The VHDL model below consists of a “main” process describing the behavior of the modeled circuit and a “test” process defining the inputs waveforms.

When this VHDL code is simulated, **what are the hexadecimal values of signal “dif” at time 50 ns, 150 ns, 250 ns and 350 ns?**

Answer with 2 hexadecimal digits for each value of “dif”, separated by a white space. Example: If the value of “dif” is A9 at t=50, B8 at t=150, 7C at t=250 and 6D at t=350ns, write A9 B8 7C 6D in the answer box.

(Note: Negative numbers are represented in 2’s complement. The 2’s complement of a number can be computed replacing 1s by 0s and 0s by 1s, and adding 1 to the result.

`1 LIBRARY IEEE;`

2 USE IEEE.STD_LOGIC_1164.ALL;

3 USE IEEE.STD_LOGIC_ARITH.ALL;

4 USE IEEE.STD_LOGIC_UNSIGNED.ALL;

5

6 ENTITY exercise1 IS

7 END exercise1;

8

9 ARCHITECTURE behavior OF exercise1 IS

10 CONSTANT max: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00001111";

11 SIGNAL a: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";

12 SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";

13 SIGNAL dif: STD_LOGIC_VECTOR(7 DOWNTO 0);

14 SIGNAL neg: STD_LOGIC;

15

16 BEGIN

17

18 main: process(a, b)

19 begin

20 if a >= b + max then dif <= max; neg <= '0'; 21 elsif a >= b then dif <= a-b; neg <= '0';

22 elsif b<=a+max then dif<=b-a;neg<='1'; else dif<=max; neg<='1';

23 end if;

24 end process;

25

26 test: process

27 begin

28 a <= "00011111";

29 b <= "00110001";

30 wait for 100 ns;

31 b <= "00101011";

32 wait for 100 ns;

33 b <= "00011011";

34 wait for 100 ns;

35 b <= "00001110";

36 wait;

37 end process;

38

39 END behavior;

Enter answer here

#### Week 5: Digital Systems: From Logic Gates to Processors

Q1. Which statement is true?:

- The memory elements with asynchronous inputs (reset and/or set) can change their state only when these signals are active.
- The duration of the positive pulse and the negative pulse of the clock signal may be different.
- The next state of memory elements depends only on the clock signal.
- The frequency of a clock signal with period T=20ns is 50KHz.

Q2. Complete the following time chart.

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop, click on Simulate->Verification and then click on the VerilChart tab.*

*2) In “Module” select “Graded Exercises”, click on exercise 5.2.b and enter the time chart.*

*3) Click on Verify (bottom-right corner). VerilChart returns a 4 uppercase letters code. Type it in the answer box.*

- UIMI
- BTJG
- ZKSK

Q3. The graph shown in figure 1 describes a 2-input (x1, x0), 1-output (Z) sequential circuit Assume that the initial state is “A” and **write the sequence of states and outputs reached by the circuit when the input pattern shown in table 1 is received.**

Note: Write the state/output pairs at t0, t1, t2 and t3, separated by a space. Example: If in t0 the circuit goes from A to C with output 0, then in t1 remains at C with output 1; in t2 changes to state D with output 0 and finally in t3 changes to state C with output 1, you should write C/0 C/1 D/0 C/1

Table 1

Figure 1

Enter answer here

Q4. We want to design a circuit that controls the opening and closing of an access gate for vehicles. The control system receives 4 input signals:

- Request: Comes from a button that the vehicle’ driver presses (Request=1) to open the gate.
- Upper: Comes from a sensor in the gate. Takes value 1 when the gate is fully open.
- Lower: Comes from a sensor in the gate. Takes value 1 when the gate is fully closed.
- Sensors: Comes from sensors located in the “gate area” (see figure). Takes value 0 when that area is free of vehicles.

The control circuit generates 2 outputs:

- ON/OFF: Motor power off (ON/OFF=0) or power on (ON/OFF=1)
- UP/DOWN: Indicates the direction of the gate movement.
- Open the gate: ON/OFF=1, UP/DOWN=0
- Close the gate: ON/OFF=1, UP/DOWN=1

The control circuit must perform the following sequence of operations:

- Wait for an access request signal (Request=1)
- Open the gate (ON/OFF=1, UP/DOWN=0)
- Wait until the gate is fully open (Upper=1)
- Wait until the gate area is clear of vehicles (Sensors=0) and begin to close the door (ON/OFF=1, UP/DOWN=1)
- Wait until the gate fully closed (Lower=1) and return to the initial state, waiting for a new “Request” signal. .

No new access request will be attended until this sequence of events is completed.

**Which of the following graphs defines the circuit?**

*(Note: Let’s see that only one signal appears on every edge. That means that the transition to the new state depends only on this signal, independently of the values of the rest of the signals)*

Figure 1

Q5. Assuming that states S0, S1 and S2 have been codified as **S0: 00; S1: 01; y S2: 11, complete the following state transition table and the output table of figure 1.**

**Be carefull with the states’ codes**

*Note: Write the table entering the “Next state” column from top to bottom, separating the states with a white space, and then the “Output” column, in the same order, with a white space between outputs. Example: Table of figure 2 should be entered as 11 11 00 00 xx xx 00 01 1 0 1 0 x x 1 0 (“x” lowercase)*

Figure 1

Figure 2

Enter answer here

Q6. **Design and draw a sequential circuit having one input X and one output Y that implements the behavior shown in table 1**.Name inputs and outputs of the circuit as shown in figure1 (X, RST, clk, Y).State S0 should be coded as 00.

**Very important note:** The VerilUOC_Desktop verifier requires that all inputs of the flip flops are connected to some value. So, it is necessary to connect “S” inputs to 0 and “load” inputs to 1. To do so, click in “wiring”, select “Constant” and connect the constant (a logical 1) to the “load” inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the “S” inputs.

Figure 1

Table 1

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.*

*2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.*

*3) In “Module” select “Graded Exercises” and click on exercise 5.6.a.*

*4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Preview will appear here…

Enter math expression here

#### Week 6: Digital Systems: From Logic Gates to Processors

Q1. Design a 4-bit shift register that can (1) shift its information at right, (2) shift its information at left and (3) asynchronously initialize to state 0000 when RST=1.

The figure below shows the circuit inputs and outputs. (Use exactly these names. Respect upper and lower case):

- clk: Input. Clock signal.
- RST: Input. Reset signal.
- N: Data input.
- SL (Shift_Left): Input. When SL=1 (and SR=0), the information moves one position at left and IN inputs to the rightmost flip flop.
- SR (Shift_Right): Input. When SR=1 (and SL=0), the information moves one position at right and IN inputs to the leftmost flip flop.
- When SR=SL=0 or SR=SL=1 the information remains unchanged.
- OUT: Output. It outputs the state of the rightmost flip flop.

Note 1: When using multiplexers from the library, set the “Include Enable?” field to **NO **to remove the “Enable” pin.

*Note 2: To properly verify the circuit, VerilUOC_Desktop requires all inputs of the flip flops are connected to some value. In this case, “S” inputs must be connected to 0. Click in “Wiring” (left menu), select “Constant” and, in the Value property replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the “S” inputs*.

Figure

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.*

*2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.*

*3) In “Module” select “Graded Exercises” and click on exercise 6.1.*

*4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q2. Design a 6-bit, shift-right register with D flip flops, and use it to implement a circuit that detects the sequence “110101” (the rightmost bit is the first arriving). Information shifts one position right when a positive edge of clk occurs.The circuit has the following inputs and outputs (use exactly these names for inputs and outputs. Respect upper and lower case):

- clk: Input. Clock signal.
- RST: Reset signal. When RST = 1 flip flops are reset to 0.
- IN: Data entry. IN inputs to the leftmost flip flop at each rising edge of clk.
- OUT: Output. Takes the value 1 when the last bit of sequence 110101 is detected (see example) and returns to 0 in the next clock cycle.

N*ote:To properly verify the circuit, VerilUOC_Desktop requires all inputs of the flip flops are connected to some value. So, it is necessary to connect “S” inputs to 0 and “load” inputs to 1. To do so, click in “Wiring” (left menu), select “Constant” and connect the constant (a logical 1) to the “load” inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the “S” inputs.*

Example:

*Instructions to answer this question*

*1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.*

*2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.*

*3) In “Module” select “Graded Exercises” and click on exercise 6.2.b*

*4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q3. Outputs of binary counters are square signals whose frequencies are sub-multiples of the main clock (\small{clk}clk) frequency. Based on this fact, counters are often used to generate clock signals of different frequencies. Let’s consider a 4-bits, binary up-counter with outputs \small{q3}q3, \small{q2}q2, \small{q1}q1 and \small{q0}q0 (\small{q3}q3 is the most significant bit). If the main clock signal (clk) has a frecuency of 2MHz, **which will be the frequency of output signal \small{q1}q1?.**

- 4 MHz
- 1 MHz
- 500 KHz
- 250 KHz

Q4. Design a 2-bit binary, cyclic up-counter and use it to implement a circuit that generates continuously the sequence 1001 and displays it by the output OUT (the leftmost bit of the sequence is generated when the counter is in the initial state 00). The counter increases by 1 at every positive edge of the clock signal.The final circuit will have the following inputs and outputs (use exactly these names for inputs and outputs):

- clk: Input. Clock signal.
- RST: Reset signal. When RST = 1 the counter is reset to 00.
- OUT: Output.

Note 1: All flip flops must be synchronized by the “clk” signal (For experts: do not use “ripple-counter” or similar architectures)

*Note 2: To properly verify the circuit, VerilUOC_Desktop requires all inputs of the flip flops are connected to some value. So, it is necessary to connect “S” inputs to 0 and “load” inputs to 1. To do so, click in “Wiring” (left menu), select “Constant” and connect the constant (a logical 1) to the “load” inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the “S” inputs.*

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.*

*2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.*

*3) In “Module” select “Graded Exercises” and click on exercise 6.4.a*

*4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q5. Module COUNT is a 3-bit binary up-counter with parallel load. While “load”=0, counter increases by 1 each time a positive edge of clk occurs. If “load”= 1, entries are loaded into the counter at the next positive edge. **Complete the time chart for the circuit in figure 1.**

Note that the circuit generates a cyclic output sequence y1, y0 = (0, 1, 3, 3, 2) by using a 3-bit counter with “synchronous reset” (“synchronous reset” means that counter is set to 0 when “load”=1 **and **a positive clock edge occurs)

**Instructions to answer this question**

*1) In the virtual machine, open VerilUOC_Desktop, click on Simulate->Verification and then click on the VerilChart tab.*

*2) In “Module” select “Graded Exercises”, click on exercise 6.5.a and enter the time chart.*

*3) Click on Verify (bottom-right corner). VerilChart returns a 4 uppercase letters code. Type it in the answer box.*

Enter answer here

Q6. Which of the following statements are true? Check all that apply.

- DRAM basic cell has fewer transistors than the SRAM one and therefore, DRAM memories may have a larger storage capacity than the SRAM memories.
- DRAM memories retain information even when no power is supplied because they incorporate circuitry that periodically refreshes the information.
- OTP ROM can be programmed up to 128 times.
- A 220 x 16 words memory requires a 20-to-220 address decoder
- A 220 x 16 words memory has a 16-bit data bus and a 220-bit address bus.
- In a Read/Write memory, bit-lines transmit the information to be stored in memory cells, while word-lines transmit the Read/Write command.

#### Week 7: Digital Systems: From Logic Gates to Processors

Q1. VHDL processes of Figure 1 describe the operation of a movement-direction detector similar to that studied in lecture L7.3. It is assumed that we have previously defined the inputs “x” (2-bit signal whose components are x(1), x(0)), “clk” and “reset”; the output “z” and the signals “cs” and “nextState”, which can take the values (0,1,2,3).

We want to design a sequential circuit that implements this motion detector, and to do so we have thought in using a block design as the one shown in Figure 2: The second block contains a 2-bit register storing the internal state of the circuit (nextState), and the first block contains a combinational circuit responsible for calculating (1) the next state (nextState) from the current state (cs) and the inputs (x), and (2) the output “z”, also from the current state and inputs.

**Mark which of the following circuit implements the “COMBINATIONAL CIRCUIT” module of Figure 1.**

Note: In the circuits shown as solutions, the “x2” symbol framed in a square or circle means that the input or output signal has 2 bits. The “x1” symbol means that the signal has 1 bit.

Figure 1: VHDL code.

`1 synchronization: process (reset, clk)`

2 begin

3 if reset = '1' then cs <= 0; 4 elsif clk'event and clk = '1' then cs<=nextState; 5 end if; 6 end if; 7 end process synchronization; 8 9 mov_det: process (cs, x) 10 begin 11 nextState <= cs; 12 case cs is 13 when 0 => z <= x(1); 14 case X is 15 when 1 => nextState := 1;

16 when 3 => nextState := 3;

17 end case;

18 when 1 => z <= not(x(0); 19 case X is 20 when 2 => nextState := 0;

21 when 3 => nextState := 2;

22 end case;

23 when 2 => z <= not(x(1)); 24 case X is 25 when 0 => nextState := 1;

26 when 2 => nextState := 3;

27 end case;

28 when 3 => z <= x(0); 29 case X is 30 when 0 => nextState := 0;

31 when 1 => nextState := 2;

32 end case;

33 end case;

34 end process mov_det;

Figure 2: Block diagram of the circuit

Q2. Given an n-bit natural X and an integer E represented under the form (-1)SIGN.|E|, the shifting algorithm shown in figure 1 computes an n-bit natural M such that

- When E ≥ 0, E trailing zeroes are added and E leading bits are removed.
- When E < 0, |E| leading zeroes are added and |E| trailing bits are removed.

Example (n = 14):

If X = 01110111010010 and E = 5 then M=11101001000000;

If X = 01110111010010 and E = -5 then M=00000011101110;

Figure 2 shows a sequential machine that implements this algorithm for **n=4 **and |**E**|**=3**, where:

M and next_M are 4-bits numbers; count and next_count are 2-bits numbers and done and next_done are 1-bit numbers.

The bits of M, next_M, count and next_count are named as follows: M = {M3, M2,M1,M0}>; next_M = {next_M3,next_M2,next_M1,next_M0}; count={count1,count0}; next_count={next_count1,next_count0}

When reset=1, count, M and done are respectively set to |E|, X and 0. **What are the Boolean functions for next_count and next_done?**

```
1 M <= X; done <= 0; count <= |E|;
2 loop
3 if (count > 0) and (done = 0) then
4 if SIGN=0 then M<=M(n-2 downto 0)&0; -- (Note1)
5 else M<=0&M(n-1 downto 1); -- (Note2)
6 end if;
7 else done <= 1;
8 end if;
9 if done=0 then count <= count - 1; end if;
10 end loop;
11
----------
12 -- Note1: This sentence computes M<=M•2 by shifting the bits of
13 -- M one position left and setting M(0)=0.
14 -- Note2: This sentence computes M<=M/2 by shifting the bits of
15 -- M one position right and setting M(n-1)=0.
----------
```

Figure 1

Figure 2

Q3. **EXERCISE 7.3.b: **The VHDL codes associated with every answer can be found in file quiz7.pdf included in “Reading : QUIZ 7 INSTRUCTIONS”.

A **queue **(figure1) is a memory that works as follows:

if a write_request is received, then data_in is “pushed into” the queue;

if a read_request is received, then data_out is “pulled out” of the queue.

We want to model the queue in VHDL by using a single “process”. For that we use:

An array stored_data that represent the data stored within the queue; it has n components {stored_data(0),stored_data(1), … , stored_data(n-1)};

A natural variable write_address that points to the component of array stored_data where the next data should be stored,

A natural variable read_address that points to the component of array stored_data that should be pulled out,

A natural number, named number, equal to the number of data in the queueA binary variable (flag) empty>, equal to “true” if all data have been pulled out of the queue, and

A binary variable (flag) full, equal to “true” if all n queue positions are occupied.

Assume that a write operation will never be requested when the queue is full and a read operation will never be requested when the queue is empty. Assume also that there are never simultaneous read and write requests.

**Select the VHDL code that describes this queue.**

*Note: conv_integer(x) converts x to an integer. Zero and one are previously defined constants equal to 0 and 1 respectively. Max_number_minus_1 is the size of the queue minus 1 (max_number_minus_1=n-1).*

Figure 1

- CODE 5
- CODE 6
- CODE 7
- CODE 8

Q4. **EXERCISE 7.4.a: **The VHDL codes associated with every answer can be found in file quiz7.pdf included in “Reading : QUIZ 7 INSTRUCTIONS”.

A **stack **(figure1) is a memory that works as follows:

- if a write_request is received, then data_in is “pushed into” the stack;
- if a read_request is received, then data_out is “pulled out” of the stack.

We want to model the stack in VHDL by using two processes. The first one describes a Moore finite state machine that controls the sequence of operations, and where its output state is equal to its internal state. The second defines the operations. For that we use :

- An array stored_data that represents the data stored within the stack. Stored_data has n components: {stored_data(0),stored_data(1), … , stored_data(n-1)}
- A natural variable address that points to the component of array stored_data where the next data should be stored,
- A binary variable (flag) empty, equal to “true” if all data have been pulled out of the stack, and
- A binary variable (flag) full, equal to “true” if all n stack positions are occupied.

Assume that a write operation will never be requested when the stack is full and a read operation will never be requested when the stack is empty. Assume also that there are never simultaneous read and write requests.

**Select the VHDL code that describes this stack.**

Note: conv_integer(x) converts x to an integer. Zero and oneare previously defined constants equal to 0 *and 1 respectively. Max_address is the size of the stack (max_address=n)*

Figure 1

- CODE 9
- CODE 10
- CODE 11
- CODE 12

Q5. **EXERCISE 7.5:** The VHDL codes associated with every answer can be found in file quiz7.pdf included in “Reading : QUIZ 7 INSTRUCTIONS”.

We want to define a finite state machine (FSM) that controls the execution of a two-branch process (figure 1):

On a positive edge of start, if branch_selection = 0 then the control signal branch_1 goes high and the processor starts executing the first branch;

If branch_selection = 1 then the control signal branch_2 goes high and the processor starts executing the second branch.

When the processor completes its task (first or second branch), it raises the signal (flag) done.

Then, the control signal branch_1 or branch_2 (the one that has been raised) goes low, the processor lowers done, and the control circuit waits for another positive edge on start.

**Select the VHDL code that models the FSM “control”.**

Figure 1

- CODE 17
- CODE 18
- CODE 19

#### Week 8: Digital Systems: From Logic Gates to Processors

Q1. Mark the true statements.

- PCB is an acronym of “Printed Circuit Board”
- Big digital circuits (say circuits containing more than 100,000 gate-equivalent devices) must be implemented first with SSI or MSI chips to check their functionality.
- Any digital circuits can be implemented with Standar Cells or Gate Arrays, but this approach uses to be poorly efficient when the circuit is small, with low performance, or when the required productIon is low.
- The 7400 chip contains 4 2-inputs NAND gates. Such a chip is considered a small scale integration (SSI) circuit.

Q2. Mark the true statement.

- The aim of Microelectronics is the study and implementation of analog and digital circuits within semiconductors materials, most frequently Silicon.
- Only digital circuits can be implemented by using Microelectronic processes.
- The aim of Microelectronics is the study and implementation of circuits containing an extremely small number of transistors.
- The aim of Microelectronics is the study and implementation of analog and digital circuits by using very tiny discrete components (resistors, capacitors, transistors…).

Q3. Mark the true statements.

- Integrated circuits are manufactured in special rooms called “Clean Rooms”.
- Silicon wafers are thin plates of semiconductor material on which the integrated circuits are built.
- Clean Rooms have equipment to ensure that the number of particles suspended in the air is below a certain threshold. This level of cleanness is essential for the production of integrated circuits.
- Masks are used to define over which regions of a wafer a particular process will be applied to.
- A microelectronic technology is a set of technological processes (such as ion implantation, oxidation, deposition or etching) that can be applied on a semiconductor material (usually silicon) in a particular order to obtain an integrated circuit.
- In current microelectronic technologies, the area occupied by a transistor is typically of the order of milimeters2.

Q4. Mark the statements concerning Standard Cells which are true.

- Macrocells are special library cells that implement, in general, more complex functions than logic gates or bistables. In many cases, libraries contain configurable macrocells such that the designer can define some of their parameters (for instance, number of words and bit/word of a memory block, length of a shift register, etc.).
- In the Standard Cell approach, library cells are places in rows separated by routing channels. In some cases, cells cover the silicon surface completely and interconnection layers pass over them.
- Standard Cells use a library of cells where the layout of all cells has the same height and the same width.
- Gate Arrays have better performances, in terms of integration density, speed and consumption, than Standard Cells.
- FPGAs have better performances, in terms of speed and consumption, than Standard Cells.
- Macrocells are special library cells such that the designer can define their height and width.

Q5. Mark the statements concerning Gate Arrays which are true.

- Gate Arrays have better performances, in terms of integration density, speed and consumption, than Standard Cells.
- There exist computer-aided design (CAD) tools that automatically create the layers required to transform the uncommitted cells of a Gate Array into the desired logic component (gates, memory elements, etc.)
- In the first Gate Arrays, uncommitted cells were placed in rows separated by routing channels. In the current Gate Arrays, the uncommitted cells occupy all the silicon surface and the interconnection layers pass over the cells.
- Gate Arrays are based on the existence of uncommitted cells on the silicon surface that must be customized to form the desired gates or memory elements.
- Gate Arrays are usually less expensive than Standard Cells because a part of their layout (the part corresponding to the uncommitted cells) is already defined and is identical for all users. This reduces the number of masks needed in the manufacturing process, thus lowering the cost.
- Gate Arrays have better performances, in terms of speed and consumption, than FPGAs.

Q6. Mark the statements concerning FPGAs which are true.

- The customization (programming, configuration) process of the basic blocks and the interconnections of a FPGA can be performed in the designer’s laboratory.
- FPGAs consist of a set of basic blocks and interconnections layers that can be customized.
- FPGAs must be programmed (customized) in the foundry. The advantage of FPGAs regarding Gate Arrays and Standard Cells is that this customization process is faster and less expensive.
- The basic blocks are identical for all the FPGAs.
- FPGAs are particularly suitable when the number of units to be implemented is very high (let’s say over 20,000 units).
- FPGAs are particularly suitable for the implementation of prototypes and small series.

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